The following workshops will be offered at FPL 2015:
W1: ReC4P 2015 – First International Workshop on Reconfigurable Computing for HPC and HPDA
|
Date |
Monday 31 August 2015 |
|
Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 |
|
Location |
Imperial College London Electrical Engineering room 611 |
Description
Accelerators implemented on reconfigurable logic appear to be a promising platform to increase efficiency of high-performance computing (HPC) systems. Through specialisation, hybrid systems composed of general-purpose processors and reconfigurable devices, such as FPGAs, configured to accelerate specific kernels of applications can achieve speed-ups of orders of magnitude with limited power consumption. Scientific simulations, which employ regular computation, have high arithmetic intensity and present easily partitionable datasets, can easily benefit from application-specific accelerators.
On the other hand, a new class of emerging applications is appearing. This class includes the big field of data analytics applications (e.g. analysis of social networks, security, transportation and communications networks, finance databases, bio-informatics and healthcare, open government, the semantic Web, data mining, language understanding and pattern recognition).
All of these applications have different characteristics and behaviours from conventional HPC applications (typically, scientific simulations). However, they still require high-performance computing systems to provide results in a timely fashion. Furthermore, they are all experiencing exponential growths in the availability of data (i.e. big data challenges). For this reason, they have started to be identified as high-performance data analytics (HPDA) applications.
There still are significant gaps between the complexity and variety of HPC and HPDA applications, and the potential benefits provided by custom accelerators. The objective of the ReC4P workshop is to identify the breakthroughs required to make reconfigurable logic applicable to HPC and HPDA applications. The intended audience of the workshop includes researchers from industry, academia and government for the area of reconfigurable computing.
More information on ReC4P 2015 can be found .
Organisers
| Antonino Tumeo (Pacific Northwest National Laboratory, US) | |
| Gianluca Palermo (Politecnico di Milano, IT) |
|
W3: FSP 2015 – Second International Workshop on FPGAs for Software Programmers
|
Date |
Tuesday 1 September 2015 |
|
Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 12:30 – 13:30 Lunch 13:30 – 15:00 Part 3 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 4 |
|
Location |
Imperial College London Electrical Engineering room 611 |
Description
The aim of this workshop is to make FPGAs and reconfigurable technology accessible to software programmers. Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists. With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken. In the second edition of the FSP workshop, we will in particular focus on success stories where FPGAs had been exploited by software engineers.
The FSP Workshop aims to bring researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends. This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardised target platforms. This will in particular put focus on the requirements of software developers and application engineers. In addition, a distinctive feature of the workshop will be its cross-section through all design levels, ranging from programming down to custom hardware. Thus, the workshop is targetting all of those interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development. In addition, the FSP Workshop shall facilitate collaboration between the different domains.
Topics of the FSP workshop will include, but not be limited to:
- High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems
- Mapping approaches and tools for heterogeneous FPGAs
- Support of hard IP blocks such as embedded processors and memory interfaces
- Development environments for software engineers (automated tool flows, design frameworks and tools and tool interaction)
- FPGA virtualisation (design for portability, resource sharing and hardware abstraction)
- Design automation technologies for multi-FPGA and heterogeneous systems
- Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility, reliability or programmability
- Operating system services for FPGA resource management, reliability and security
- Targetted hardware design platforms (infrastructure, drivers and portable systems)
- Overlays (CGRAs, vector processors and ASIP- and GPU-like intermediate fabrics)
- Applications (e.g. embedded computing, signal processing, bio-informatics, big data, database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc.
- Directions for collaborations (research proposals, networking and Horizon 2020)
More information on FSP 2015 can be found here.
Organisers
| Tobias Becker (Maxeler, UK) | |
| Frank Hannig (Friedrich-Alexander-Universität Erlangen-Nürnberg, DE) | |
| Dirk Koch (University of Manchester, UK) | |
| Daniel Ziener (Friedrich-Alexander-Universität Erlangen-Nürnberg, DE) |
W4: RC4Masses – Workshop on Reconfigurable Computing for the Masses, Really?
|
Date |
Friday 4 September 2015 |
|
Times |
10:40 – 10:50 Opening remarks 10:50 – 11:30 Invited talk 1: Jim Larus (École Polytechnique Fédérale de Lausanne, CH) 11:30 – 12:10 Invited talk 2: Kunle Olukotun (Stanford University, US) 13:30 – 15:00 Workshop session 1: 'New Opportunities' 15:00 – 15:30 Coffee break 15:30 – 17:00 Workshop session 2: 'Software Environments' 17:00 – 18:30 Round table and panel discussions |
|
Location |
Royal Institution Theatre (morning) Imperial College London Electrical Engineering room 408 (afternoon & evening) |
Description
Reconfigurable computing has been around almost as long as FPGAs themselves. Yet, very few FPGAs populate data centres, even fewer are on acceleration boards in our PCs, and none are in our laptops or tablets. We are now witnessing a new and exciting inflection point in the use of FPGAs: they are now being viewed as potentially viable commercial off-the-shelf components directly in the path of software developers. Microsoft recently revealed Catapult, a server with FPGAs soon to be in use in large data centres to accelerate their Bing search engine. Intel have announced a new compute node that will integrate an FPGA with a large Xeon multi-core processor. These types of announcements show industrial commitment to accelerate the transition of FPGAs into new application domains dominated by software programmers.
Enabling software developers to apply their skills to FPGAs has been a long and, as of yet, unreached research objective in reconfigurable computing. In the past, our inability to reach this goal did not greatly impact the adoption of FPGAs within the traditional markets of embedded and networking systems. However, the additional engineering effort and extended time to market required is clearly not an option when FPGAs are to be integrated in conventional computing equipment.
Obstacles to widespread FPGA adoption go well beyond the required skill set. Another major obstacle is the total lack of standardisation. A moderately experienced software programmer can be evaluating and testing basic ideas literally within hours from project start. Contrast this with someone interested in accelerating a computing job with FPGAs: devices across vendors are fundamentally different and incompatible; RTL programs, albeit in principle portable, are definitely not; development software is completely vendor-specific, with very significant differences in feature sets and often with a level of robustness well below common software standards and getting even the simplest host-to-FPGA communication functionality may take weeks, even for skilled designers. Porting a software project across devices or even boards using the same device may take from weeks to months before meaningful experimentation might start, even for experimented designers. Using GPUs as accelerators has some aspects in common with using FPGAs but the overall experience has been made to resemble much more that of a software job. Will this ever happen for FPGAs? Can reconfigurable computing become mainstream if the fundamentally limiting factors of required skill sets and of solidity of the programming ecosystem are not solved?
More information on RC4Masses can be found here.
Organisers
| Paolo Ienne (École Polytechnique Fédérale de Lausanne, CH) | |
| David Andrews (University of Arkansas, US) | |
| Walid Najjar (University of California Riverside, US) |
W5: WCS-IoT 2015 – First International Workshop on Components and Services for IoT platforms
|
Date |
Friday 4 September 2015 |
|
Times |
10:40 – 10:50 Opening remarks 10:50 – 11:30 Invited talk 1 11:30 – 12:10 Invited talk 2 13:30 – 15:00 Workshop session 1 15:00 – 15:30 Coffee break 15:30 – 17:00 Workshop session 2 |
|
Location |
Royal Institution Conversation Room (morning) Imperial College London Electrical Engineering room 611 (afternoon) |
Description
The Internet of Things (IoT) is an evolving trend which will cover the whole world and requires the most efficient technology that has ever been produced. This is because the IoT enables all kinds of smart objects (e.g. smart sensors and actuators) to communicate and interact with each other across different networks and domains. A plethora of new services and applications are or must be created revealing the potential to create substantial new markets and to stimulate existing ones. However, it is also quite clear that on the way to a fully connected cyber-physical world numerous challenges have to be addressed. As with every new technology wave, we are witnessing a debate regarding industry standards striving to find a position in the IoT marketplace.
The WCS-IoT workshop intents to foster dialogue and interaction among researchers from academia and industry, addressing the contemporary challenges in IoT platforms, services, tools, programming languages and applications. In particular, special emphasis will be given to whether the current or under-development IoT standards meet the specifications of the IoT-related considerations like low-power, time-to-market, connectivity, reliability, interoperability, security and privacy. Do we need new IoT standardisation bodies or initiatives? Finally, as part of this workshop, the outcomes of current European research projects related to IoT platforms, services, APIs, tools and applications are welcomed to be presented. New possibilities for synergies between European companies and research institutions will be explored in the context of future European-funded projects.
The Internet of Things (IoT) is upon us! Current forecasts predict that there will be more than 50 billion devices connected to the Internet by 2020, and this is just the beginning.
Topics of the WCS-IoT workshop will include, but not be limited to:
- Platforms for IoT services
- IoT and CPS (cyber-physical systems) hardware architectures
- Low-power and reconfiguration techniques for the IoT
- Energy- and resource-efficient connectivity solutions
- Programming languages and APIs for the IoT
- New IoT applications or re-evaluation of existing ones
- Secure IoT and CPS architectures
- Sensor and actuator technologies
- New (business) use-cases for the IoT
- The role of semantics and middleware in IoT technology
- User interfaces for IoT devices
- Support of self-management and plug-and-play mechanisms
More information on WCS-IoT 2015 can be found here.
Organisers
| Michael Hübner (Ruhr-Universität Bochum, DE) | |
| Nikolaos Voros (Technological Educational Institute of Western Greece, GR) | |
| Georgios Keramidas (Technological Educational Institute of Western Greece, GR) |
