The following tutorials will be offered at FPL 2015:
T1: NetFPGA – Rapid Prototyping of High-bandwidth Devices in Open Source
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Date |
Monday 31 August 2015 |
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Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 |
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Location |
Imperial College London Electrical Engineering room 1109 |
Description
NetFPGA is an open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. NetFPGA is the de-facto experimental platform for line-rate implementations of network research and has a family of boards, supporting from 1GE to 100GE. This half-day tutorial will provide an introduction to prototyping and using networking devices on the NetFPGA platform, and discuss considerations in architecture and design for high-bandwidth devices.
The demand-led growth of cloud computing and data centre networks has meant that many constituent technologies are beyond the budgets of the research community. In order to make and validate timely, relevant research contributions, the wider research community requires accessible evaluation, experimentation and demonstration environments with specifications comparable to the subsystems of the largest data centre networks.
The NetFPGA platform can be used by researchers to prototype advanced services for next-generation networks. It can also be used in the classroom to teach students how to build Ethernet switches and Internet Protocol (IP) routers using hardware rather than software. The most prominent NetFPGA success is OpenFlow, which in turn has reignited the software-defined networking movement. NetFPGA enabled OpenFlow by providing a widely available open-source development platform capable of line-rate operation and was, until its commercial uptake, the reference platform for OpenFlow.
This tutorial will focus on rapid prototyping of high-bandwidth devices using flexible, open-source IPs. It will present NetFPGA SUME, an open-source FPGA-based PCIe board designed for the research community. NetFPGA SUME has I/O capabilities for 100Gbps operation as a networking device, standalone computing unit or for test and measurement. In addition we will also present the NetFPGA-1G-CML platform, which enables complex designs for low-bandwidth applications, and is especially suited for network-security applications.
The tutorial will provide a hands-on example, giving the participants an opportunity to experience the prototyping of a working hardware networking application. It will also provide a live demonstration of a 100Gbps high-bandwidth networking switch.
The target audience is not restricted to networking researchers: NetFPGA represents the ideal platform for research across a wide range of topics from computing architecture to algorithms and energy-efficient design to hardware accelerators. It is thus ideally suited to the attendees of FPL. No knowledge of Verilog or VHDL is required to attend the tutorial, although knowledge of these languages is needed to program NetFPGA.
Outline
- Introduction to NetFPGA
- Users (researchers and professors)
- What is NetFPGA?
- Boards
- Tools & reference designs
- Contributed projects
- Community
- Hardware overview
- NetFPGA SUME
- Field-programmable gate array (FPGA) logic
- Random access memory (RAM)
- SPF+ interfaces
- PCIe interface
- Expansion interfaces
- Storage
- NetFPGA-1G-CML: high-level overview
- NetFPGA SUME
- Example 1: Basic functionality – packet filtering
- Header lookup and filtering
- Hands-on experience
- Example 2: 100Gbps Ethernet switch
- Brief introduction to 100Gbps
- FPGA design for high-bandwidth architectures
- 100Gbps Ethernet switch architecture
- Demonstration
- Where to get started/what to do next
- Web page
- Wiki
- Forums
More information on NetFPGA can be found here.
Presenters' Biographies
Andrew Moore is a senior lecturer at the University of Cambridge Computer Laboratory in Cambridge, UK, where he is part of the Systems Research Group and leads work on reconfigurable network systems. He has over two decades' experience working on networked systems monitoring, characterisation and emulation. He was joint investigator of the NSF-funded NetFPGA project, investigator on the EPSRC programme grant INTERNET, principal investigator on EPSRC NAAS and investigator on the DARPA-funded CTSRD and MRC2 projects. Previously an EPSRC Roberts Fellow and an Intel Research Fellow, Andrew has ongoing financial support from Xilinx, Ensoft and Solarflare, with past support from AT&T, Microsoft, NetApp, Chelsio, Broadcom, Red-Gate, Cisco and SolarFlare. Andrew has a PhD in network systems from the University of Cambridge. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.
Noa Zilberman is a research associate at the University of Cambridge Computer Laboratory in Cambridge, UK. She has over 15 years of industrial experience in the telecommunication and semiconductor industries. In her last role, Noa was a senior principal chip architect in Broadcom's Network Switching group. She was a teaching assistant and a lecturer at Tel-Aviv University, teaching the Computer Architecture and Computer Networks undergraduate courses. During her time at the industry, Noa was an instructor in several customer-training programmes. She has conducted numerous NetFPGA camps and introductory sessions. Noa is a senior member of IEEE, a member of the ACM and has a PhD in Electrical Engineering from Tel-Aviv University.
Yury Audzevich is a research associate at the University of Cambridge Computer Laboratory in Cambridge, UK. He is an expert on energy-efficient designs for high-bandwidth networking devices, and was the lead researcher of CONTEST (CONfigurable Transceiver Energy uSage Toolkit). Previously, he was an Alcatel-Lucent research associate at the University of Trento. Yury has been a guest lecturer and teaching assistant in several courses, both at the University of Cambridge and University of Trento, since 2007. He has conducted numerous NetFPGA camps and introductory sessions. Yury obtained his PhD in Information and Telecommunication Technologies from the University of Trento.
T2: Rapid Development of Real-time Applications with National Instruments LabVIEW
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Date |
Monday 31 August 2015 |
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Times |
13:30 – 15:00 Part 1 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 2 |
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Location |
Imperial College London Electrical Engineering room 1109 |
Description
The ability to rapidly move from high-level concept to real-world system has never been more important as effective time-to-market constraints continue to shrink. As a result, FPGAs are now spanning the space from prototype to end systems as custom hardware designs are no longer feasible in many domains. While chip vendor tools have made great strides in recent years in making FPGA programming within the reach of software developers, a significant barrier still exists when moving algorithms from software to hardware.
The integrated hardware and software platform from National Instruments (NI) can shorten the design, simulation and deployment cycle by providing tools for floating-point simulation, floating-point to fixed-point conversion, hardware and software partitioning, performance-complexity trade-offs and, finally, verification and testing on an FPGA platform.
This tutorial introduces the design flow offered by LabVIEW Communications System Design Suite through a series of exercises in which attendees will move an application from concept to implementation. No previous experience with NI hardware or software is required. Minimal FPGA design experience will be helpful but is also not required.
Outline
- Overview of NI LabVIEW Communications System Design Suite & NI USRP RIO
- System architecture definition
- System designer tool
- Reference designs and sample projects
- Initial floating-point algorithm development
- MathScript and C Nodes
- Multi-rate diagram
- Unit testing
- Preparing a design for deployment to an FPGA
- Fixed-point conversion
- System testbenches
- Design-space exploration
- FPGA simulation
- FPGA compilation
More information on LabVIEW can be found here.
Presenter's Biography
Dustyn Blasig is a member of the Advanced Development Group at National Instruments, specialising in the design of the language and compilers necessary to effectively and efficiently target various hardware platforms, including more than a decade of work with FPGAs. He contributed to the design and implementation of many of the topics discussed in this tutorial. Dustyn received his BSEE and MSEE from the University of Texas at Austin.
T3: Underneath the FPGA Clothes – Enhancing Security
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Date |
Tuesday 1 September 2015 |
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Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 |
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Location |
Imperial College London Electrical Engineering room 1109 |
Description
FPGAs are primarily digital devices and application designers have to follow the usual design methodologies of digital systems when they target FPGAs. Nevertheless, when the applications include cryptographic primitives, these methodologies are not sufficient to achieve the security requirements of certification. The variability of parameters of the devices, due to electronic noise, ageing, environmental fluctuations and CMOS/FLASH process variations conduce to change the design methodologies and the designers have to consider analogue phenomena during the design of the digital system. At the same time, the continuous increase in the number of research projects on hardware implementation of ciphers, true random number generators (TRNGs) and physically unclonable functions (PUFs) highlights their scientific and practical interest. But design, evaluation and test of such cryptographic primitives are arduous, especially in FPGAs when the designer doesn't control all of the design parameters and the estimation of entropy sources is tricky. This half-day tutorial will provide an introduction to the physical phenomena for the security of digital integrated circuits, including introductions to randomness generation, device fingerprint generation and to the protection of cryptographic primitives against physical attacks.
Random numbers are crucial in cryptography: they are used as confidential keys, initialisation vectors, nonces in challenge-response protocols, padding values, hardware identifiers, and as masks in side channel attack countermeasures. Random number generators (RNGs) and physically unclonable functions (PUFs) must generate random numbers that have good statistical properties and the generated sequences must be impossible to predict and manipulate. To help FPGA designers with TRNG/PUF design and evaluation, we will discuss the design, statistical evaluation and tests of TRNGs and PUFs when implemented in FPGAs.
This tutorial is suited for all attendees of FPL. No preliminary knowledge of cryptographic engineering or embedded system security is needed.
Outline
- Physical phenomena impacting the security of digital integrated circuits
- A digital circuit is, after all, an analogue circuit
- Physical phenomena impacting security
- Randomness generation and entropy sources
- Device fingerprint (PUF) generation
- Protection against physical attacks
- Random number generation for cryptography
- Introduction to random number generation
- Entropy extraction, statistical models and entropy estimators
- Post-processing
- RNG testing
- State of the art and pitfalls in TRNG designs
- Practical example: design and evaluation of a secure TRNG
- Design and characterisation of a PUF in an FPGA
- Introduction to physically unclonable functions
- Architectures of silicon PUFs
- FPGA-oriented designs of efficient PUFs
- Comprehensive example of PUF design and characterisation in an FPGA
Presenters' Biographies
Viktor Fischer received his MS and PhD degrees in Electrical Engineering from the Technical University of Kosice in Slovakia. From 1981 to 1991 he held an assistant professor position at the Department of Electronics at the Technical University of Kosice. From 1991 to 2006 he was a part-time invited professor at the University of Saint-Etienne, France. From 1999 to 2006 he was also a consultant for Micronic Slovakia, oriented in hardware data security systems. From 2006 he has been a full professor at the University of Saint-Etienne. His research interests include cryptographic engineering, secure embedded systems, cryptographic processors and especially true random number generators embedded in logic devices. He is the co-founder and a senior member of the CryptArchi club.
Lilian Bossuet received an MS degree in Electrical Engineering from INSA, Rennes, France and a PhD in Electrical Engineering and Computer Sciences from the University of South Britanny, Lorient, France. From 2005 to 2010, he was an associate professor and the head of the Embedded System Department in the Bordeaux Institute of Technologies. Since 2010, he has been an associate professor at the University of Saint-Etienne and a member of the Hubert Curien Laboratory. He holds the special CNRS (Centre National de la Recherche Scientifique) Chair of Applied Cryptography and Embedded System Security. His main research activities focus on embedded systems hardware security, IP protection, crypto-processor design and reconfigurable architecture. Lilian has published over 110 refereed publications in these areas and is a senior member of the IEEE and a senior member of the CryptArchi Club.
Jean-Luc Danger is a full professor at TELECOM ParisTech. He is the head of the Digital Electronic System research group in the Communications and Electronics department. He notably conducts research in the fields of security for embedded systems, configurable architectures and implementation of complex algorithms for telecommunications. Jean-Luc has authored around 200 scientific publications and patents in architectures and the security of embedded systems, and he is a co-founder of the Secure-IC, where he is a scientific advisor. He received his engineering degree in Electrical Engineering from Ecole Supérieure d'Electricité in 1981. After 12 years in industrial laboratories with Philips and Nokia, he joined TELECOM ParisTech in 1993, where he received the full professor title in 2002. He is a senior member of the IEEE, senior member of the CryptArchi Club and editor of the Journal of Cryptographic Engineering.
T4: The LEAP Run-time System – Rapid System Integration of Your HLS Kernels
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Date |
Tuesday 1 September 2015 |
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Times |
13:30 – 15:00 Part 1 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 2 |
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Location |
Imperial College London Electrical Engineering room 1109 |
Description
Do you find yourself bogged down in FPGA plumbing, focussed on the mechanics of moving data instead of on your algorithms? Are you using an HLS compiler but tired of building FPGA-side memory hierarchies? These problems are not unique to hardware. Analogous software problems were solved decades ago. We don't manage locks for shared memory access directly in Python. Developers compose Python with complex underlying primitives that are debugged once and shared across languages. High-level languages are great for expressing abstract programs. A full system also requires glue logic and low-level, high-performance components.
The LEAP operating environment for FPGAs provides composable components and services for algorithms spanning one or more FPGAs and for hybrid algorithms combining FPGAs and software. LEAP APIs remain consistent across a variety of platforms, enabling application portability. LEAP separates the problem of specifying an algorithm from the problem of building a supporting runtime system. The LEAP programming model allows both hand-coders and HLS compiler users to focus on their own applications.
Current HLS systems typically provide very simple FPGA-side memory subsystems and little support for I/O outside of shared memory. This is due, in large part, to the complexity of building more flexible, application-specific environments. In addition to the topics below, we will discuss the value of library-based cache construction and describe the interfaces through which HLS-generated kernels are supported by LEAP-generated, application-specific memory hierarchies.
The LEAP environment is open source (BSD license). Though the LEAP operating system is written in Bluespec System Verilog, user code may be written in any synthesisable language.
This half-day tutorial will cover:
- Building algorithms using latency-insensitive design
- Passing messages through LEAP named connections
- Replacing block RAM with LEAP memory services (cached virtual memory and optional cross-FPGA coherent caches)
- Connecting to host files using LEAP STDIO
- Debugging applications using automatically generated and formatted state dumps
- Connecting HLS-generated kernels to LEAP-generated, application-specific complex cache hierarchies
- Installing a virtual machine and walking through compiling a sample application
More information on LEAP can be found here.
Presenters' Biographies
Michael Adler is a member of the Technology Pathfinding and Innovation (TPI) group at Intel. After beginning his career on compiler back-ends he has moved down the hierarchy towards processor simulation and microarchitecture research. His research is focused on the challenges of rapid specification of complex reconfigurable systems.
Kermin Fleming is a member of the Technology Pathfinding and Innovation (TPI) group at Intel. His work is focussed mainly on tools and techniques for implementing high-performance reconfigurable systems and architectures.
Hsin-Jung Yang is a PhD candidate in the Department of Electrical Engineering and Computer Science at MIT. She previously received a BS degree from National Taiwan University and an SM degree from MIT. Her research interests include high-performance architectural design for reconfigurable computing.
Felix Winterstein is a PhD candidate at Imperial College London. His research interests include high-performance computing using reconfigurable logic and high-level synthesis with an emphasis on compiler-based memory optimisations.
