The keynotes at FPL 2015 will be as follows:
Extending the Power of FPGAs to Software Developers – Salil Raje (Xilinx, US)
| Date | Wednesday 2 September 2015 |
| Time | 09:00 – 10:00 |
| Location | Royal Institution Theatre |
| Session chair | Wayne Luk (Imperial College London, UK) |
| Slides | Click here to view |
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Audio recording |
Currently unavailable |
FPGAs have evolved from simple programmable logic arrays to complex SoCs with millions of programmable elements. As the FPGA device has evolved, so has the programming paradigm. The industry has made significant progress in raising the abstraction level of FPGA design by leveraging a large set of IP blocks, enabling abstract IP integration, and exploiting high-level synthesis technology that allows users to work at the algorithmic level. While these innovations have increased the productivity of FPGA designers, they have not unleashed the full potential of FPGAs to the software programmers of the world. If we are intent on expanding the reach of FPGAs, we need to drive towards fully software-programmable FPGAs that can be used for heterogeneous computing. The programming solution needs to have the same look and feel as standard IDEs and abstract away the complexities of the underlying hardware while exploiting the massive parallelism of FPGAs for hardware acceleration. Key to enabling the era of software programmability will be the concept of the programmable platform – an abstraction that will allow the FPGA to take on the persona of the application domain. The journey to embrace the software developer community has begun.
Salil Raje is Corporate Vice President of Software and IP Products Development at Xilinx, where he has held a variety of roles in the development organisation since 2004. Prior to joining Xilinx, he was the founder and CTO of Hier Design, an EDA startup focussed on hierarchical design methodology and design planning tools for the FPGA market. Prior to that, Salil was a director at Monterey Design Systems, an EDA startup working on place and route technology for standard-cell ASIC design. Salil began his career at IBM Research Center at Yorktown Heights, New York, working on high-level synthesis. He holds a BTech in Electrical Engineering from IIT, Madras and an MS and a PhD in Computer Science from Northwestern University.
Applications of FPGAs to the Financial Trading Industry – David Lariviere (Columbia University, US)
| Date | Wednesday 2 September 2015 |
| Time | 13:00 – 14:00 |
| Location | Royal Institution Theatre |
| Session chair | Wayne Luk (Imperial College London, UK) |
| Slides | Withheld |
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Audio recording |
Withheld |
Programmable logic is having a profound and increasingly dominant role in modern financial markets. This talk will present an overview of electronic trading systems, trends in the underlying technologies, and explore areas of opportunity for researchers and industry to become more involved.
Professor David Lariviere teaches at Columbia University in the City of New York as an adjunct professor in the Departments of Computer Science and Electrical Engineering. His research focusses on the application of next-generation technologies towards the intersection of electronic trading and ultra low-latency packet processing. In industry, Prof. Lariviere is a consulting expert in the electronic trading space, architecting systems responsible for safely and quickly processing packets worth trillions of dollars daily.
Architectural Paths to Faster and More Robust FPGAs – Mike Hutton (Altera, US)
| Date | Thursday 3 September 2015 |
| Time | 09:00 – 10:00 |
| Location | Royal Institution Theatre |
| Session chair | Peter Cheung (Imperial College London, UK) |
| Slides | Click here to view |
|
Audio recording |
Click here to listen |
For most of the 25 years of the FPL Conference, FPGA technology has successfully ridden Moore's Law to greater density, higher performance and lower power. We're still getting density and power benefits, but more performance is required by the end markets and spending more power to get there isn't acceptable. On other fronts: the need for memory is growing but we don't get more pins for DDR, and development effort and complexity is also increasing, making it harder to build a single device where everything just works first time and inside a reasonable budget. When you can't count on only riding the process curve, architecture needs to come to the rescue! In this presentation, I will highlight several fundamental changes for FPGAs that are introduced in the new Stratix 10 family: (1) HyperFlex – a fresh re-design of routing fabric architecture allowing logic to be heavily pipelined without resource penalties and targetting twice the performance of existing FPGAs; (2) modularity and software-controlled FPGA configuration – allowing independent housekeeping and re-configuration for device sectors; and (3) extensive use of 3D integration across Intel's embedded multi-die interconnect bridge (EMIB) technology – allowing not just in-package memory and heterogeneous devices but mixed-process development to de-risk and optimise analogue and digital design on different technology processes.
Mike Hutton is an IC design architect at Altera and principal investigator in the Altera Technology Office. He is responsible for product architecture definition for new devices, most recently the Stratix 10 family, and research within the Technology Office. He received a BMath and MMath in Computer Science from Waterloo and a PhD from the University of Toronto. He is Associate Editor of IEEE Trans. CAD, past Programme and General Chair of the Int'l Symposium on FPGAs and has served on the Technical Programme Committees for many research conferences, including DAC, DATE, FPGA, FPL and FPT.
European High-performance Computing Strategy and Outlook – Panagiotis Tsarchopoulos (European Commission, BE)
| Date | Thursday 3 September 2015 |
| Time | 13:00 – 13:50 |
| Location | Royal Institution Theatre |
| Session chair | Cristina Silvano (Politecnico di Milano, IT) |
| Slides | Withheld |
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Audio recording |
Withheld |
The talk will provide detailed information on the current status and perspectives for high-performance computing research in Horizon 2020. It will also summarise the outcomes of recent European HPC calls for proposals. The talk will give an overview of forthcoming research funding opportunities in the overall Future and Emerging Technologies programme of H2020.
Panagiotis Tsarchopoulos is responsible for high-performance computing research at the Future and Emerging Technologies unit of the European Commission. Dr Tsarchopoulos holds a PhD in computer engineering from the University of Kaiserslautern, Germany and an MBA from the UBI, Brussels, Belgium.
Field-programmable Neurocomputing – Steve Furber (University of Manchester, UK)
| Date | Friday 4 September 2015 |
| Time | 09:00 – 10:00 |
| Location | Royal Institution Theatre |
| Session chair | Peter Cheung (Imperial College London, UK) |
| Slides | Click here to view |
|
Audio recording |
Click here to listen |
SpiNNaker is a massively parallel computer system, ultimately to incorporate a million ARM processor cores (the largest machine to date has 100,000 cores) with an innovative, lightweight packet-switched communications fabric capable of supporting typical biological connectivity patterns in biological real time. One of the key principles in the design of SpiNNaker, based on the observation that different brain regions have different connectivity patterns, is to virtualise topology, effectively decoupling the topology of the network being modelled from the topology of the machine itself. As a result, SpiNNaker can be viewed as a large field-programmable neurocomputer, where the neural circuit can be configured flexibly at run-time. The network can be described using a neural HDL such as PyNN or Nengo, and then the design tools compile the network onto the machine where it runs in biological real time.
Steve Furber CBE FRS FREng is ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester, UK. After completing a BA in mathematics and a PhD in aerodynamics at the University of Cambridge, UK, he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor. Over 60 billion variants of the ARM processor have since been manufactured, powering much of the world's mobile and embedded computing. He moved to the ICL Chair at Manchester in 1990 where he leads research into asynchronous and low-power systems and, more recently, neural systems engineering, where the SpiNNaker project is delivering a computer incorporating a million ARM processors optimised for brain modelling applications.
