The technical sessions for FPL 2015 will be as follows:
Applications 1: Linear Algebra and Control Applications
| Date | Wednesday 2 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Theatre |
|
Session chair |
Dirk Koch (University of Manchester, UK) |
10:40 – 11:00
Efficient Assembly for High-order Unstructured FEM Meshes
Pavel Burovskiy, Paul Grigoras, Spencer Sherwin and Wayne Luk
11:00 – 11:20
A Scalable FPGA Architecture for Non-negative Least Squares Problems
Alric Althoff and Ryan Kastner
11:20 – 11:40
Towards Heterogeneous Solvers for Large-scale Linear Systems
Stylianos Venieris, Grigorios Mingas and Christos-Savvas Bouganis
11:40 – 12:00
A Software Configurable Coprocessor-based State-space Controller
Aaron Mills, Pei Zhang, Sudhanshu Vyas, Phillip Jones and Joseph Zambreno
Architectures & Technology 1: Energy-efficient and Low-power Architectures
| Date | Wednesday 2 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Conversation Room |
|
Session chair |
Jason Anderson (University of Toronto, CA) |
10:40 – 11:00
Automatic Generation of High-throughput Energy-efficient Streaming Architectures for Arbitrary Fixed Permutations
Ren Chen and Viktor Prasanna
11:00 – 11:20
Using Island-style Bi-directional Intra-CLB Routing in Low-power FPGAs
Oluseyi Ayorinde, He Qi, Yu Huang and Benton Calhoun
11:20 – 11:40
Energy Optimization of FPGA-based Stream-oriented Computing with Power Gating
Mohammad Hosseinabady and Jose Nunez-Yanez
11:40 – 12:00
Energy-efficient Partitioning of Dynamic Reconfigurable MRAM-FPGAs
Ali Ahari, Mojtaba Ebrahimi and Mehdi Tahoori
Design Methods & Tools 1: Parallelism and Logic Design
| Date | Wednesday 2 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Demo Room |
|
Session chair |
Dirk Stroobant (Universiteit Gent, BE) |
10:40 – 11:00
Automatic Support for Multi-module Parallelism from Computational Patterns
Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun and Paolo Ienne
11:00 – 11:20
ParaLaR: A Parallel FPGA Router Based on Lagrangian Relaxation
Chin Hau Hoo, Akash Kumar and Yajun Ha
11:20 – 11:40
Fine-tuning CLB Placement to Speed Up Reconfigurations in NVM-based FPGAs
Yuan Xue, Patrick Cronin, Chengmo Yang and Jingtong Hu
11:40 – 12:00
A Technology Mapper for Depth-constrained FPGA Logic Cells
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Liqun Yang, Zhihong Huang, Haigang Yang and Paolo Ienne
Applications 2: Computer Vision and Numerical Applications
| Date | Thursday 3 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Theatre |
|
Session chair |
Tobias Becker (Maxeler Technologies, UK) |
10:40 – 11:00
A Deep Convolutional Neural Network using Nested Residue Number System
Hiroki Nakahara and Tsutomu Sasao
11:00 – 11:20
Fast Hierarchical Implementation of Sequential Tree-reweighted Belief Propagation for Probabilistic Inference
Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José Martínez and Rob Rutenbar
11:20 – 11:40
A Scalable Pipelined Architecture for Biomimetic Vision Sensors
Daniel Llamocca and Brian Dean
11:40 – 12:00
FPGA Implementation to Estimate the Number of Endmembers in Hyperspectral Images
Carlos Gonzalez, Sebastian Lopez, Daniel Mozos and Roberto Sarmiento
Architectures & Technology 2: Cryptography and Security Architectures
| Date | Thursday 3 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Conversation Room |
|
Session chair |
Guy Gogniat (Université de Bretagne Sud, FR) |
10:40 – 11:00
Compact Dual-block AES core on FPGA for CCM Protocol
João Resende and Ricardo Chaves
11:00 – 11:20
Towards Efficient Discrete Gaussian Sampling for Lattice-based Cryptography
Chaohui Du and Guoqiang Bai
11:20 – 11:40
An Efficient Many-core Architecture for Elliptic Curve Cryptography Security Assessment
Marco Indaco, Fabio Lauri, Andrea Miele and Pascal Trotta
11:40 – 12:00
High-speed ECC Implementation on FPGA over GF(2m)
Zia Khan and Mohammed Benaissa
Design Methods & Tools 2: Accelerators and High-level Synthesis
| Date | Thursday 3 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Demo Room |
|
Session chair |
Fabrizio Ferrandi (Politecnico di Milano, IT) |
10:40 – 11:00
SPINE: From C Loop-nests to Highly Efficient Accelerators using Algorithmic Species
Mark Wijtvliet, Shakith Fernando and Henk Corporaal
11:00 – 11:20
Optimised OpenCL Workgroup Synthesis for Hybrid ARM-FPGA Devices
Mohammad Hosseinabady and Jose Nunez-Yanez
11:20 – 11:40
CoRAM++: Supporting Data Structure-specific Memory Interfaces for FPGA Computing
Gabriel Weisz and James Hoe
11:40 – 12:00
Scavenger: Automating the Construction of Application-optimized Memory Hierarchies
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein and Joel Emer
Applications 3: Pattern-matching and Search Applications
| Date | Thursday 3 September 2015 |
| Time | 14:00 – 15:00 |
| Location | Royal Institution Theatre |
|
Session chair |
Kubilay Atasu (IBM, CH) |
14:00 – 14:20
Power-efficient Range Match-based Packet Classification on FPGA
Yun Qu and Viktor Prasanna
14:20 – 14:40
A Variable-length Hash Method for Faster Short Read Mapping on FPGA
Yoko Sogabe and Tsutomu Maruyama
14:40 – 15:00
Hybrid Breadth-first Search on a Single-chip FPGA-CPU Heterogeneous Platform
Yaman Umuroglu, Donn Morrison and Magnus Jahre
Architectures & Technology 3: Reconfigurable Computing and Architectures
| Date | Thursday 3 September 2015 |
| Time | 14:00 – 15:00 |
| Location | Royal Institution Conversation Room |
|
Session chair |
Cathal McCabe (Xilinx, IE) |
14:00 – 14:20
A Fully Pipelined Kernel-normalised Least Mean Squares Processor For Accelerated Parameter Optimisation
Nicholas Fraser, Duncan Moss, Jun-Kyu Lee, Stephen Tridgell, Craig Jin and Philip Leong
14:20 – 14:40
An Efficient Reconfigurable Architecture by Characterizing Most Frequent Logic Functions
Iman Ahmadpour, Behnam Khaleghi and Hossein Asadi
14:40 – 15:00
Static Hardware Task Placement on Multi-context FPGA using Hybrid Genetic Algorithm
Hao Liang, Sharad Sinha, Rakesh Warrier and Wei Zhang
Design Methods & Tools 3: Simulation and Emulation
| Date | Thursday 3 September 2015 |
| Time | 14:00 – 15:00 |
| Location | Royal Institution Demo Room |
|
Session chair |
Marco Platzner (Universität Paderborn, DE) |
14:00 – 14:20
Domain-specific Optimisation for the High-level Synthesis of CellML-based Simulation Accelerators
Julian Oppermann, Andreas Koch, Ting Yu and Oliver Sinnen
14:20 – 14:40
Software-in-the-loop Simulation of Embedded Control Applications based on Virtual Platforms
Stephan Werner, Leonard Masing, Fabian Lesniak and Jürgen Becker
14:40 – 15:00
Ultra-fast NoC Emulation on a Single FPGA
Thiem Van Chu, Shimpei Sato and Kenji Kise
Applications 4: High-level Synthesis and Optimisation
| Date | Thursday 3 September 2015 |
| Time | 15:40 – 17:00 |
| Location | Royal Institution Theatre |
|
Session chair |
Blair Fort (Altera, US) |
15:40 – 16:00
From Low-architectural Expertise Up to High-throughput Non-binary LDPC Decoders: Optimization Guidelines using High-level Synthesis
Joao Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne and Gabriel Falcao
16:00 – 16:20
A study of Data Partitioning on OpenCL-based FPGAs
Zeke Wang, Bingsheng He and Wei Zhang
16:20 – 16:40
Limits of FPGA Acceleration of 3D Green's Function Computation for Geophysical Applications
Nachiket Kapre, Selvakumar Jayakrishnan, Parjanya Gupta, Sagar Masuti and Sylvain Barbot
16:40 – 17:00
Recursive Pipelined Genetic Propagation for Bilevel Optimisation
Shengjia Shao, Liucheng Guo, Ce Guo, Thomas Chau, David Thomas, Wayne Luk and Stephen Weston
Architectures & Technology 4: Architectures and Synthesis
| Date | Thursday 3 September 2015 |
| Time | 15:40 – 17:00 |
| Location | Royal Institution Conversation Room |
|
Session chair |
Andreas Herkersdorf (Technische Universität München, DE) |
15:40 – 16:00
Synthesizable FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD
Jin Hee Kim and Jason Anderson
16:00 – 16:20
Hoplite: Building Austere Overlay NoCs for FPGAs
Nachiket Kapre and Jan Gray
16:20 – 16:40
FPGA-based Low-overhead Speculative Addition for Signed Operands (slides withheld)
Alessandro Cilardo
16:40 – 17:00
Inter-procedural Resource-sharing in High-level Synthesis through Function Proxies
Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo and Fabrizio Ferrandi
Design Methods & Tools 4: Hybrid FPGA-based Systems
| Date | Thursday 3 September 2015 |
| Time | 15:40 – 16:40 |
| Location | Royal Institution Demo Room |
|
Session chair |
Walid Najjar (University of California Riverside, US) |
15:40 – 16:00
Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Challenges & Directions
Meena Belwal, Madhura Purnaprajna and Sudarshan TSB
16:00 – 16:20
Hybrid FPGA Debug Approach
Zdravko Panjkov
16:20 – 16:40
A High-performance Protocol for Exposing IP Cores as Functions in a Shared-bus SoC
David Thomas, George Constantinides, Shane Fleming and Ivan Beretta
Architectures & Technology 5: Memory Management and Customised Architectures
| Date | Friday 4 September 2015 |
| Time | 10:40 – 12:00 |
| Location | Royal Institution Demo Room |
|
Session chair |
Ioannis Sourdis (Chalmers Tekniska Högskola, SE) |
10:40 – 11:00
SysAlloc: A Hardware Manager for Dynamic Memory Allocation in Heterogeneous Systems
Zeping Xue and David Thomas
11:00 – 11:20
Efficient Data-Stream Management for Shared Memory Many-core Systems
Nuno Neves, Pedro Tomás and Nuno Roma
11:20 – 11:40
A Scalable Architecture for Multi-class Visual Object Detection
Siddharth Advani, Yasuki Tanabe, Kevin Irick, Jack Sampson and Vijaykrishnan Narayanan
11:40 – 12:00
Enhancing Stochastic Computations via Process Variation
Rui Duarte, Mário Véstias and Horácio Neto
