The following industrial workshops will be offered at FPL 2015:
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IW1: Xilinx System Design with Zynq IW2: Overview of Altera's Cyclone V SoC Devices and Design Tools IW3: Xilinx SDSoC: Building Software-defined Systems-on-Chip with Zynq All-programmable SoCs |
IW1: Xilinx System Design with Zynq
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Date |
Monday 31 August 2015 |
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Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 12:30 – 13:30 Lunch 13:30 – 15:00 Part 3 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 4 |
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Location |
Imperial College London Electrical Engineering room 507 |
Description
This course provides professors with a fast introduction to system design using the ARM-based Xilinx Zynq All-programmable SoC, Vivado, IP Integrator and Vivado HLS. Vivado IP Integrator is the Xilinx system-level design tool that enables rapid design of complex FPGA SoCs. Vivado HLS accelerates IP creation by enabling C, C++ and System-C specifications to be directly targetted into Xilinx All-programmable devices without the need to manually create RTL.
During the hands-on labs, attendees will get the opportunity to try out the Vivado design flow for Zynq, including the creation of programmable logic accelerators using HLS.
Who should attend?
Professors who are familiar with Xilinx All-programmable technology and wish to get up-to-speed with SoC-based system design using Zynq and HLS.
Prerequisites
- Digital logic and FPGA design experience
- Basic understanding of the C programming and embedded design
Skills to be gained
- Understand how to architect an embedded system targetting the ARM processor of Zynq using Vivado and IP Integrator
- Extend the hardware system with Xilinx-provided peripherals
- Create a custom peripheral in programmable logic and add it to the system
- Use Vivado HLS to generate an IP-XACT-compliant hardware accelerator and interface it with the system
Outline
- XUP/AUP introduction
- Zynq introduction and the Vivado design flow
- Lab 1: Create a processor system using IP Integrator
- Create a simple ARM Cortex-A9-based processor design targetting Zynq using IP Integrator
- Embedded system design with custom IP
- Lab 2: Creating and adding your own custom IP
- Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral. Write a basic C application to access the peripheral
- Introduction to high-level synthesis with Vivado HLS
- Improving performance and resource utilisation
- Lab 3: Creating a processor system using an accelerator
- Profile an application performing a function both in software and hardware
- Create an accelerator in Vivado HLS
- Use the generated accelerator to build a complete system
- Lab 4: ARM demonstration using DS5 to target Zynq
- Closing session: Q&A
IW2: Overview of Altera's Cyclone V SoC Devices and Design Tools
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Date |
Tuesday 1 September 2015 |
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Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 12:30 – 13:30 Lunch 13:30 – 15:00 Part 3 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 4 |
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Location |
Imperial College London Electrical Engineering room 304 |
Description
This workshop will provide an overview of the SoC FPGA devices that are part of the Altera Cyclone V family. The workshop is split into four topics which are listed below along with details of the material to be covered. Participants will gain hands-on experience building embedded systems using Altera's software tools and the DE1-SoC board.
Outline
- ARM bare-metal programming
- Introduction to the Cyclone V Hard Processor System (HPS) with ARM Cortex-A9
- Introduction to ARM Assembly Language
- Compiling assembly and C-language programs
- Communicating between ARM programs and FPGA-side components
- Using Linux with Altera SoC devices
- Compiling Linux programs
- Programming the FPGA from Linux
- Communicating between Linux programs and FPGA-side components
- Creating Linux drivers for FPGA components
- Altera OpenCL SDK
- Overview
- Writing an OpenCL application
- Optimising Altera OpenCL designs
- Altera FPGA architecture design methodology
- A discussion on Altera's process of next-generation architecture development
IW3: SDSoC: Building Software-defined Systems-on-Chip with Zynq All-programmable SoCs
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Date |
Tuesday 1 September 2015 |
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Times |
09:00 – 10:30 Part 1 10:30 – 11:00 Coffee break 11:00 – 12:30 Part 2 12:30 – 13:30 Lunch 13:30 – 15:00 Part 3 15:00 – 15:30 Coffee break 15:30 – 17:00 Part 4 |
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Location |
Imperial College London Electrical Engineering room 507 |
Description
The Zynq-7000 all-programmable SoCs enable extensive system-level differentiation, integration and flexibility through hardware, software and I/O programmability. This hands-on workshop covers the development of high-performance ARM + FPGA applications using Zynq devices, working entirely within a software development environment. After a very brief introduction to the Zynq architecture, we will focus on the application development process using SDSoC to target heterogeneous compute platforms like Zynq. Lab exercises will reintroduce attendees to the familiar design steps of identifying program hot-spots, optimizing code to improve performance and cross-compiling the application and running on the target with the less familiar outcome of using SDSoC to build not just the application binaries, but also hardware accelerators in programmable logic that communicate with the CPU and external memory through an application-specific data motion network comprised of DMAs, interconnects and other standard IP blocks. We will see how to instrument code to measure application performance and how this can be used to estimate overall speed-up of moving code from software into programmable logic. To demonstrate that the programming model and workflows are agnostic to the target run-time environment, attendees will build, debug, and run embedded systems running Linux and bare-metal over the course of the day.
Who should attend?
Professors who are familiar with Xilinx all-programmable technology and wish to find out about the new SDSoc design methodology.
Prerequisites
- Digital logic and FPGA design experience
- Basic understanding of the C programming and embedded design
Skills to be gained
- Learn how to rapidly architect bare-metal and Linux embedded systems targetting the Xilinx all-programmable Zynq SoC using Xilinx SDSoc
- Understand the methods available to identify software hotspots and measure system performance
- Implement hardware accelerators and custom IP for a Zynq embedded system using the SDSoc flow
- Build bare-metal and Linux images and test on hardware
