The poster sessions for FPL 2015 will be as follows:
PhD Forum
| Date | Wednesday 2 September 2015 |
| Time | 10:00 – 10:40 |
| Location | Royal Institution Georgian Room |
|
Session chair |
Andy Tyrell (University of York, UK) |
Greedy Approach-based Heuristics for Partitioning SpMxV on FPGAs
Jiasen Huang, Weina Lu and Junyan Ren
Scheduling-aware Interconnect Synthesis for FPGA-based Multi-processor System-on-Chip
Edoardo Fusella, Alessandro Cilardo and Antonino Mazzeo
Rapid Prototyping and Design Space Exploration Methodologies for Many-accelerator Systems
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos and Dimitrios Soudris
Towards a Guided Design Flow for Heterogeneous Reconfigurable Architectures
Timm Bostelmann and Sergei Sawitzki
High-level Synthesis Extensions for Scalable Single-chip Many-accelerators on FPGAs
Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios and Dimitrios Soudris
FPGA-based All-digital Software-defined Radio Receiver
André Prata, Arnaldo Oliveira and Nuno Carvalho
Over Effective Hard Real-time Hardware Tasks Scheduling and Allocation
Zakarya Guettatfi, Omar Kermia and Abdelhakim Khouas
FPGA-based All-digital Transmitters
Rui Cordeiro, Arnaldo Oliveira and José Vieira
A Framework for Integrated Monitoring of Real-time Embedded SoC
Giacomo Valente
Applications
| Date | Wednesday 2 September 2015 |
| Time | 15:00 – 15:40 |
|
Location |
Royal Institution Georgian Room |
An FPGA Implementation of a Phylogenetic Tree Reconstruction Algorithm Using an Alternative Second-pass Optimization
Henry Block and Tsutomu Maruyama
Ultra Low-latency Dataflow Renderer
Sebastian Friston, Anthony Steed, Simon Tilbury and Georgi Gaydadjiev
Exploring with Pipe Implementations using an OpenCL Framework for FPGAs
Vincent Mirian and Paul Chow
Parallel Feature Extraction and Heterogeneous Object Detection for Multi-camera Driver Assistance Systems
Stefan Wonneberger, Peter Muehlfellner, Pedro Ceriotti, Thorsten Graf and Rolf Ernst
A Transport Layer Network for Distributed FPGA Platforms
Sang-Woo Jun, Ming Liu, Shuotao Xu and Arvind Arvind
Generating FPGA Accelerators for Chemical Similarity Assessment
Nikolaos Alachiotis
rrBox: A Remote Dynamically Reconfigurable Network-processing Middlebox
Tze Tan, Chia Ooi and Nadzir Marsono
FPGA-based Nonlinear Support Vector Machine Training Using an Ensemble Learning
Mudhar Rabieah and Christos-Savvas Bouganis
Architectures & Technology
| Date | Thursday 3 September 2015 |
| Time | 10:00 – 10:40 |
|
Location |
Royal Institution Georgian Room |
Optimizing Energy-efficient Low-swing Interconnect for Sub-threshold FPGAs
He Qi, Oluseyi Ayorinde, Yu Huang and Benton Calhoun
An Automated Technique to Generate Relocatable Partial Bitstreams for Xilinx FPGAs
Roel Oomen, Tuan Nguyen, Akash Kumar and Henk Corporaal
Pipelined and Customized NoC Router Architecture Design on FPGA
Qi Chen and Qiang Liu
Accurate Power Analysis for Near-Vt RRAM-based FPGA
Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli
OpenCL Computing on FPGA Using Multi-ported Shared Memory
Tahsin Türker Mutlugün and Sheng-De Wang
Adaptive MRAM-Based CGRAs
Xiaobin Liu, Tedy Thomas, Alan Boguslawski and Russell Tessier
Reduction Calculator in an FPGA-based Switching Hub for High-performance Clusters
Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa and Hideharu Amano
Serial and Parallel Interleaved Modular Multipliers on FPGA Platform
Khalid Javeed, Xiaojun Wang and Mike Scott
Data Protection Using Recursive Inverse Function
Teng Xu, Hongxiang Gu and Miodrag Potkonjak
Design Methods & Tools
| Date | Thursday 3 September 2015 |
| Time | 15:00 – 15:40 |
|
Location |
Royal Institution Georgian Room |
In-field Vulnerability Analysis of FPGA-realized Computer Vision Applications
Ioannis Chadjiminas, Christos Kyrkou, Christos Ttofis, Theocharis Theocharides and Maria Michael
A Rapid Prototyping Framework for Nano-photonic Accelerators
Alberto Garcia-Ortiz, Wolfgang Büter, A. Ali, S. Mahmood, S. Arefin, V. Sreenivas and R. Bergman
Fast FPGA System for Microarchitecture Optimization on Synthesizable Modern Processor Design
Libo Huang, Yongwen Wang, Qiang Dou, Caixia Sun, Chengyi Zhang and Chao Xu
An LZ77-style Bit-level Compression for Trace Data Compaction
Kai-Uwe Irrgang and Thomas Preußer
Mind The (Synthesis) Gap: Examining Where Academic FPGA Tools Lag Behind Industry
Eddie Hung
Rapid Evaluation of FPGA Architecture Routability Without Benchmarks
Oleg Petelin and Vaughn Betz
Temperature-triggered Behavioral IPs Hardware Trojan Detection Method with FPGAs
Xiaotong Li and Benjamin Schafer
Estimating Circuit Delays in FPGAs after Technology Mapping
Berg Severens, Elias Vansteenkiste, Karel Heyse and Dirk Stroobandt
Self-aware & Adaptive Systems
| Date | Friday 4 September 2015 |
| Time | 10:00 – 10:40 |
|
Location |
Royal Institution Georgian Room |
A Run-time Interpretation Approach For Creating Custom Accelerators
Sen Ma, Zeyad Aklah and David Andrews
Data-triggered Breakpoint for In-circuit Debug without Re-implementation
Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba and Kaoru Kawamura
Characterisation of Feasibility Regions in FPGAs Under Adaptive DVFS
Nizar Dahir, Pedro Campos, Gianluca Tempesti, Martin Trefzer and Andrew Tyrrell
A Resilient, Flash-free Soft Error Mitigation Concept for the CBM-ToF Read-out Chain via GBT-SCA
Andrei-Dumitru Oancea, Christian Stuellein, Jano Gebelein and Udo Kebschull
UniStream: A Unified Stream Architecture Combining Configuration and Data Processing
Jian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip Leong and Lingli Wang
Placing Partially Reconfigurable Stream-processing Applications on FPGAs
Nicolae Grigore and Dirk Koch
A Portable Open-source Controller for Safe Dynamic Partial Reconfiguration on Xilinx FPGAs
Jan Andersson, Stefano Di Carlo, Paolo Prinetto and Pascal Trotta
