MIPSfpga Workshop
Thank you for your interest in MIPSfpga. Registration for the workshop is now closed.

FPL 2015 is pleased to invite all delegates to attend the Imagination University Programme MIPSfpga workshop, being held at Imperial College London on Monday 7 and Tuesday 8 September 2015. Information about the workshop is available below or in PDF format.

Introduction

The Imagination University Programme is pleased to host a series of one-day workshops specifically for teachers based on the new MIPSfpga core. MIPSfpga is the RTL source code of the MIPS microAptiv for implementation on an FPGA. It is a member of the same family found in many embedded devices, including the popular PIC32MZ microcontroller from Microchip and Samsung's new Artik1. This workshop will show you how to use this core as part of a computer architecture course, which will pave the way for your students to use it in their projects, in effect creating their own SoC designs. With its long heritage and excellent documentation, MIPS is the preferred choice of RISC architecture for many teachers around the world. But in the past, to demonstrate key concepts, teachers had to settle on creating partial "MIPS-like" cores or using unofficial copies of dubious heritage. Not now! MIPSfpga is the real, "industrial" RTL, non-obfuscated, and available freely for academic use. These workshops are part of a global programme of events to enable teachers to harness this wonderful technology. You can be among the first to get hands-on with MIPSfpga!

Content

  1. Welcome & Introduction to the Imagination University Programme (IUP)
  2. Introduction to MIPSfpga
  3. MIPSfpga and Vivado Demonstration:
    1. Simulation: Incrementing LEDs program
    2. Incrementing LEDs delay program on the Nexys 4 DDR
    3. Synthesising cores on the Nexys4 DDR
    4. Codescape MIPS SDK: using Codescape to develop & debug C and assembly code
    5. Bus Blaster/OpenOCD: using the Bus Blaster JTAG probe and OpenOCD to debug a target system
  4. Lab 1: Writing C code
  5. Lab 2: Adding a 7-segment display I/O
  6. Integrating Xilinx IP blocks with MIPSfpga
  7. Porting to other boards, e.g. Digilent's Basys3
  8. Teaching Materials for MIPSfpga/wrap-up/Q&A

After your day of training you will be proficient in porting MIPSfpga to a suitable platform and aware of its potential to revolutionise your teaching of computer architecture. All delegates will be given access to the MIPSfpga core, the full Getting Started guide (written by Sarah Harris with contributions from Xilinx), detailed reference documentation about MIPS microAptiv and other vital information/programs that enable the whole package to work effectively.

Trainers

Sarah Harris (University of Nevada at Las Vegas and co-author of companion textbook Digital Design & Computer Architecture)
Cathal McCabe (Xilinx)
Daniel Chaver (Univ. Complutense de Madrid)
Munir Hasan (Imagination Technologies)
Enrique Sedano (Imagination Technologies

Preparation

To participate in these hands-on exercises, attendees will need to bring a Windows laptop. Installing Xilinx Vivado (free Webpack Edition) and Imagination's Codescape MIPS SDK (free online edition) in advance will save time on the day.

Eligibility

These workshops are free of charge for members of academia but places are limited and demand will be strong, so please apply for your place quickly. Please do not apply if you are not sure you can attend.

  • These workshops are open to academic faculty members, with a priority for those involved directly in teaching.
  • We reserve the right to accept or refuse registrations based on our desire to enable the broadest spectrum of universities and colleges to participate.
  • Prior experience of Vivado or Codescape MIPS SDK are useful but not essential.